1. Field
The present disclosure relates to a method of making an organic light-emitting display device, and more particularly, to impurity doping process during manufacture of an organic light-emitting display device.
2. Description of the Related Art
The rapid development of the information and technology (IT) industry is dramatically increasing the use of display devices. Recently, there have been demands for display devices that are lightweight and thin, consume low power and provide high resolution. To meet these demands, liquid crystal displays or organic light-emitting displays using organic light-emitting characteristics are being developed.
Organic light-emitting displays, which are next-generation display devices having self light-emitting characteristic, have better characteristics than liquid crystal displays in terms of viewing angle, contrast, response speed and power consumption, and can be manufactured to be thin and lightweight since a backlight is not required.
An organic light-emitting display includes a substrate having a pixel region and a non-pixel region and a container or another substrate which is placed to face the substrate for encapsulation and attached to the substrate by a sealant such as epoxy. In the pixel region of the substrate, a plurality of organic light-emitting diodes (OLEDs) are connected in a matrix pattern between scan lines and data lines to form pixels. In the non-pixel region, the scan lines and the data lines extending from the scan lines and the data lines of the pixel region, power source supply lines for operating the OLEDs, and a scan driver and a data driver for processing signals received from an external source via input pads and providing the processed signals to the scan lines and the data lines are formed.
Hereinafter, an example of a method of manufacturing an organic light-emitting display device, particularly, a bottom emission organic light-emitting display device is described with reference to FIGS. 1 through 6.
Referring to FIG. 1, a buffer layer is formed on a substrate having a pixel region, a transistor region and a capacitor region, and a silicon layer is formed on the buffer layer. Then, the silicon layer is patterned to form semiconductor layers (DR_TFT and SW_TFT) on the transistor region and form an electrode (STC) on the storage capacitor region. A gate insulating film is formed on the patterned silicon layer.
Referring to FIG. 2, a gate electrode material is provided on the entire substrate and then patterned to form a gate electrode GATE on each of the pixel region, the transistor region and the capacitor region. Next, the silicon layers DR_TFT and SW_TFT of the transistor region are doped with impurities in order to turn the silicon layers DR_TFT and SW_TFT into semiconductors. Here, the gate electrode GATE formed on the transistor region prevents a central portion of each of the silicon layers DR_TFT and SW_TFT from being doped with impurities. On the other hand, since the entire silicon layer STC of the capacitor region is covered with the gate electrode GATE, doping ions cannot penetrate into the silicon layer STC.
Referring to FIG. 3, an interlayer insulating film IDL is formed on the entire substrate and is then patterned to form an open region, which corresponds to the pixel region, and contact holes for forming source and drain electrodes S/D.
Referring to FIG. 4, the source and drain electrodes S/D is patterned on the transistor region. Then, the gate electrode GATE formed on each of the pixel region and the capacitor region is removed. Since the gate electrode GATE, which covers the silicon layer STC of the capacitor region and thus prevents the silicon layer STC from being doped as shown in FIG. 2, is removed, an additional doping process is performed to turn the silicon layer STC into an electrode.
Referring to FIG. 5, a pixel defining layer PDL is formed and then patterned to expose a transparent electrode (indium tin oxide (ITO)) of the pixel region (indicated by reference character ‘PIXEL’ in FIG. 5). The transistor region and the capacitor region are covered with the pixel defining layer PDL and thus are not exposed.
As described above, in the above example of a method of manufacturing an organic light-emitting display device, a polysilicon layer of a transistor region and a polysilicon layer of a capacitor region are doped separately through two rounds of doping. Such two rounds of doping are disadvantageous in terms of processing time and cost.
When the polysilicon layers (DR_TFT and SW_TFT) of the transistor region are doped with impurity ions, since only a gate insulating film exists on each of the polysilicon layers, a usual acceleration voltage for a doping process is used. However, when the polysilicon layer (STC) of the capacitor region is doped with impurity ions, since a gate insulating film and a transparent electrode layer (ITO) exist on the polysilicon layer, a higher acceleration voltage is required. Such use of different acceleration voltages is disadvantageous in terms of processing time and cost.
Resistance under a doped polysilicon layer tends to increase. Therefore, to reduce the resistance, a heat treatment process is additionally required after the polysilicon layers of the transistor region and the capacitor region, to which a high frequency is applied, are doped separately. The additional heat treatment process is disadvantageous in terms of processing time and cost.
As recently suggested, in order to improve a viewing angle, an anode electrode may be formed to have a multilayered structure of ITO-silver (Ag)—ITO as shown in FIG. 6, instead of a single layered structure of ITO. In this case, an Ag layer is formed on the capacitor region, in addition to a transparent electrode (ITO). Since the transparent electrode (ITO) and the metal layer are stacked on the polysilicon layer (STC) of the capacitor region, it is difficult to dope the polysilicon layer formed on the capacitor region.
The foregoing discussion in the background section is to provide general background information, and does not constitute an admission of prior art.